1. Field of the Invention
The present invention relates to the preparation of semiconductor devices, and more particularly to a method used to establish an electrical field near a surface of a semiconductor device, and in particular, a charge-coupled imaging device.
2. Description of the Prior Art
Charge-coupled devices are typically made of silicon and are used as solid-state imagers by taking advantage of the properties of a silicon crystal lattice. In the crystalline form, each atom of silicon is covalently bonded to its neighbor. Energy greater than the energy gap of about 1.1 eV is required to break a bond and create an electron hole pair. Incident electromagnetic radiation in the form of photons of wavelength shorter than 1 um can break the bonds and generate electron hole pairs.
The wavelength of incoming light and the photon absorption depth are directly related, the shorter the wavelength, the shorter the penetration depth into the silicon. Silicon becomes transparent at a wavelength of approximately 1100 nm and is essentially opaque to light at wavelengths shorter than 400 nm. High energy particles, X-rays and cosmic rays can break many thousands of bonds; therefore, excessive exposure to these can cause damage to the crystal lattice. Bonds can also be broken by thermal agitation. At room temperature, approximately 50 bonds per second per um.sup.3 are broken and recombined on a continuous basis. The rate of electron hole pair generation due to thermal energy is highly temperature-dependent and can be reduced arbitrarily through cooling.
In order to measure the electronic charge produced by incident photons, it was required to provide a means for collecting this charge. Thus, the potential well concept was developed, wherein a thin layer of silicon dioxide is grown on a section of silicon, and a conductive gate structure is formed over the oxide. The gate structure is formed in an array of columns and rows, thus making it possible, by applying a positive electrical potential to various gate elements, to create depletion regions where free electrons generated by the incoming photons can be stored.
By controlling the electrical potential applied to adjacent gates, the depletion region, or well, containing the free electrons can be caused to migrate along a column or row, so that the signal may eventually be output at the edge of the array.
Typically, the gate structure is arranged with multiple phases, particularly three phases, so that the potential wells may be easily migrated through the silicon to an output device.
In reality, the wells and the migration of the wells is not carried out along the surface of the silicon-silicon dioxide interface, but takes place in a buried channel below the surface. The buried channel is free of interference from interface states and thus assures effective charge transfer from well to well. The operation of a charge-coupled device is somewhat analogous to that of a bucket brigade circuit commonly used to delay electrical signals.
Because the charge from the wells located far from an output amplifier must undergo hundreds of transfers, the charge transfer efficiency of a charge-coupled device is most important, as is the quantum efficiency and the spectral response. These considerations are particularly important when extremely low light levels are to be sensed.
Light normally enters the charge-coupled device by passing through the gates in the silicon dioxide layer. The gates are usually made of very thin polysilicon, which is reasonably transparent to long wavelengths but becomes opaque at wavelengths shorter than 400 nm. Thus, at short wavelengths, the gate structure attenuates incoming light.
In an effort to overcome this difficulty, it has become the practice to uniformly thin a charge-coupled device to a thickness of approximately 10 um, using acid etching techniques. Using a thinned charge-coupled device, it then becomes possible to focus an image on the backside of the charge-coupled device, where there is no gate structure that will attenuate the incoming light. Thinned charge-coupled devices exhibit high sensitivity to light from the soft X-ray to the near-infrared region of the spectrum.
FIG. 1A illustrates schematically a cross-section of a typical thick-bodied charge-coupled device. The device includes a silicon body 2, a silicon dioxide layer 4 and a gate array 6 formed on the silicon dioxide layer. Incoming light is illustrated by arrows 8 as illuminating a front side of the silicon 2. FIG. 1B illustrates a cross-section of a thinned charge-coupled device with light illuminating a backside. The thinned charge-coupled device, having a thickness of approximately 10 um, has improved quantum efficiency and UV spectral response.
In order to improve the quantum efficiency of the charge-coupled device, it is desirable that the free electrons accumulate in the buried channel near the front surface of the charge-coupled device under the gate structure. It has become the practice to develop an electronic field near the rear surface of the charge-coupled device to drive electrons towards the front pixel surface, so that the free electrons may be concentrated in the buried channel. This practice is also used with thinned charge-coupled devices and in such cases, the rear surface of the device is subjected to ion implantation of, for example, boron, followed by laser annealing for full implant activation.
One difficulty that has been encountered with this practice is that the boron concentration maximum is not at the rear surface of the charge-coupled device, but rather is buried below the surface at a depth ranging from 2000 .ANG. to over 5000 .ANG.. As a result, the rear surface of the silicon is at a different potential than the sub-surface silicon. This situation may not be undesirable for front-illuminated devices or for rear-illuminated devices for light in the visible spectrum, where photon penetration is greater than 5000 .ANG.. However, for rear-illuminated devices, as wavelengths become shorter, the penetration depths shorten, and the photo-electrons see a potential barrier and are essentially driven to the rear surface, as opposed to the front surface. As a result, the quantum efficiency of the device becomes exceedingly low.
To reduce this undesirable phenomenon, ion implantation is generally carried out at low ion beam energies equal to or slightly greater than 5 keV. Such low ion beam energies result in an implantation concentration maximum nearer to the rear surface as, for example, at approximately 1500 .ANG.. However, with low implantation energies, the ion distribution profile tends to be rather broad, and a good sharp implantation distribution is not realized. Further broadening of the distribution profile occurs when the implantation is laser activated into the silicon matrix.
Using such techniques, the sub-surface maximum is satisfactory for visible light, but becomes a major concern and results in loss of quantum efficiency as wavelengths become shorter and the photon penetration depths fall below 2000 .ANG.. When this occurs, the photo-electron sees a potential wall that results in reduced quantum efficiency.
The problem of generating an electrical field at a surface of semiconductor material is encountered in many other fields of endeavor. The problem is not limited to the preparation of charge-coupled imaging devices. In the preparation of solar cells, the same difficulty is realized.
In order to more fully understand the techniques in ion implantation and the ion distribution profiles that may be generated, one may refer to the text entitled VLSI Technology, edited by S. M. Sze, and published by McGraw-Hill Book Company, and in particular, chapter 6 of said text.